FIG. 1 depicts a small portion of a conventional magnetic random access memory (MRAM) 1. The conventional MRAM 1 includes a magnetic storage cell 10 having a conventional magnetic element 12 that is typically a conventional magnetic tunneling junction (MTJ) 12, and a conventional selection device 14. Also depicted are a write word line 16, a read word line 18, and a bit line 20. Data is stored in the conventional magnetic element 12 by programming the conventional magnetic element to be in a high resistance state or a low resistance state. This programming is typically performed by applying magnetic fields from current pulses flowing in both the bit line 20 and the write word line 16. In general, the magnetic field generated by current flowing in either the bit line 20 or the write word line 16 alone is insufficient to program the conventional magnetic element 12. The conventional magnetic element 12 is read by activating the selection device 14 using the read word line 18 and driving a read current through the conventional magnetic element.
FIG. 2 depicts a larger portion of a conventional MRAM array 30 which uses multiple conventional memory cells, such as the conventional memory cell 10 depicted in FIG. 1. Referring back to FIG. 2, the conventional magnetic storage cells 10 are arranged in rows and columns. The conventional magnetic storage cells 10 are still associated with read word lines 18, write word lines 16, and bit lines 20. Also depicted are bit line selector 32, word line selector 34, first digit line selector 36, second digit line selector 38, bit and ground line selector 40, differential current sensor with current sources 42, comparator 44, reference column 46 having storage cells 10′ corresponding to the storage cells 10 and bit line 22 corresponding to the bit lines 20, and switches 48, 50, 52, 54, 56, and 58. The read word lines 18 are connected to and enabled by the word line selector 34. Each write word line 16, which may also be termed a digit line, is connected to first and second digit line selectors 36 and 38, respectively. Read word lines 18, and write word lines 16 run horizontally, while bit lines 20, which also serve as data lines, run vertically. The bit lines 20 are connected to first and second bit line selectors 32 and 40. The switches 48, 50, 52, 54, 56, and 58, at the ends of the lines 16, 18, 20, and 22 are typically transistors and connect the lines 16, 18, 20, and 22 to voltage sources, such as the power supply or ground.
During a write operation, a bit line 20 is activated and carries a current that generates a portion of the magnetic field required for switching (termed the switching field) the magnetic element 12. In addition, a corresponding write word line 16 is activated and carries a current that generates a remaining portion of the switching field. In most conventional MRAM 30, neither the magnetic field generated using the bit line 20, nor the magnetic field generated by the write word line 16 is alone sufficient to program, or switch the state of, any conventional magnetic element 12. However, in combination the bit line 20 and the write word line 16 can generate the switching field at their cross point. Consequently, a selected conventional magnetic element 12 can be written.
During a read operation, a read word line 18 and a corresponding bit line 20 containing the magnetic element to be read are activated. Only the conventional magnetic storage cell 10 at the cross point between the activated bit line 20 and the activated read word line 18 has current driven through it and, therefore, read. The resistance state of the conventional magnetic storage cell being read is compared to the reference cell 10′ using the differential current sensor 42 and the comparator 44, which compares the two current signals and produces an output Vout for memory state “1” or “0”.
Although the conventional MRAM 30 functions, one of ordinary skill in the art will readily recognize that there are drawbacks. Programming uses magnetic fields due to current driven through the corresponding lines 16 and 20. The magnetic fields are not a localized phenomenon. In addition, a relatively large current corresponding to a relatively large magnetic field is used to program the conventional magnetic storage cells 10. Consequently, the nearby cells may be disturbed or inadvertently written. As a result, performance of the conventional MRAM 10 suffers. This problem may be solved by using an advanced architecture called toggle writing. However, toggle writing requires much higher magnetic field, which utilizes a significantly higher current. Furthermore, for the conventional magnetic element 12 written using an applied field, the current required to generate the switching field increases as the width of the conventional magnetic element 12 decreased. Consequently, power consumption is greatly increased, particularly for a smaller magnetic element 12 in a higher density memory. This increased power consumption is undesirable. Moreover, toggle writing requires a read verification prior to actual writing. A total access time is, therefore, larger. This greater access time also makes toggle writing unattractive for high speed applications. In addition, the current generation memory cell size for conventional MRAM including toggle writing MRAM is close to 40f2 with f being the lithographic critical dimension. This size range is competitive with semiconductor memory SRAM in density. However, MRAM may cost more because MRAM uses five to seven more masks during fabrication than SRAM. Consequently, another mechanism for providing an MRAM is desired.
FIG. 3 depicts a small portion of a conventional spin transfer based switching random access memory (spin RAM) 70. The spin RAM 70 includes a conventional magnetic storage cell 80 including a conventional magnetic element 82 and a selection device 84, word line 86, bit line 88, and source line 90. The word line 86 is oriented perpendicular to the bit line 88. The source line 90 is typically either parallel or perpendicular to the bit line 88, depending on specific architecture used for the spin RAM 70.
The conventional magnetic element 82 is configured to be changeable between high and low resistance states by driving a spin polarized current through the conventional magnetic element 82. The spin polarized current changes state of the conventional magnetic element 82 using spin transfer effect. For example, the conventional magnetic element 82 may be a MTJ configured to be written using spin transfer. Typically, this is achieved by ensuring that the MTJ 82 has a sufficiently small cross-sectional area and that the layers of the MTJ have particular thicknesses. When the current density is sufficient, the current carriers driven through the conventional magnetic element 82 may impart sufficient torque to change the state of the conventional magnetic element 82. When a write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is driven in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
In order to program the conventional storage cell 80, the bit line 88 and the word line 86 are activated. A current is driven between the source line 90 and the bit line 88. If current is driven in one direction, for example from the source line 90 to the bit line 88, then the conventional magnetic element 82 is programmed to one of the two states. If current is driven in the opposite direction, for example from the bit line 88 to the source line 90, then the conventional magnetic element is programmed to the other of the two states.
For a read operation, the bit line 88 and the word line 86 are activated. Consequently, the selection device 84 is turned on. A read current is driven through the conventional magnetic element 82. The read current may be provided by a differential current sensor analogous to the differential current sensor 42 depicted in FIG. 2. Referring back to FIG. 3, the read current is thus provided to the bit line 88, which may have its bias voltage clamped. As a result, a high magnetoresistive signal can be obtained during sensing. In some conventional spin RAM, a reference cell (not shown in FIG. 3) may be used. In such a conventional spin RAM, a portion of the read current is provided to the conventional magnetic storage cell 80 being read and a portion of the current is provided to the reference cell. Thus, the current being sensed during a read operation is the difference between a constant supply current and the current that actually flows through the MTJ element. A comparator that is analogous to the comparator 44 of FIG. 2, compares the output of the differential current sensor to determine the state of the conventional magnetic storage cell 80. Thus, the conventional magnetic storage cell 80 can be programmed and read.
Thus, the conventional spin RAM 70 utilizes a write current driven through the magnetic element 82 in order to program data to the conventional magnetic storage cell 80. Thus, the conventional spin RAM 70 uses a more localized phenomenon in programming the conventional magnetic element 82. Thus, unlike the conventional MRAM 1/30, the conventional spin RAM 70 does not suffer from a half select write disturb problem.
Furthermore, for smaller magnetic elements 82 and, therefore, higher memory densities, the conventional spin RAM 70 uses a lower current. FIG. 4 is a graph 92 depicting a comparison between the write current for the conventional magnetic field switched MRAM 30 and for the conventional spin RAM 70. Note that the write current for toggle writing MRAM is higher than the current in FIG. 4. As can be seen from FIG. 4, for a conventional magnetic element 12/82 having width larger than two hundred nanometers, the current required for the conventional spin RAM 70 is higher than that for conventional MRAM 30. For conventional magnetic element 12/82 having a width less than two hundred nanometers, the write current for the conventional spin RAM 70 is less than for the conventional MRAM 30. Furthermore, for the conventional spin RAM 70, the write current decreases with decreasing width. Thus the spin RAM 70 possesses the desired scaling trend.
Although the conventional spin RAM 70 utilizes a lower current and a more localized programming scheme, the conventional spin RAM 70 may suffer from read disturb issues. FIG. 5 is a graph 94 depicting conventional spin RAM 70 write and read current distributions. The distribution 95 is a write current distribution having a minimum current I1. The distribution 96 is a reading current distribution used for the low resistance state of the conventional magnetic element 82 and having a maximum current I2. The distribution 97 is a read current distribution used for the high resistance state of the conventional magnetic element 82 and having a maximum current I3. The difference between the maximum reading current, in the distribution 96, and the minimum write current, in the distribution 95, represents the read and write margin. Stated differently, after many read cycles, it may be possible for a read current, such as the current I2, to inadvertently write to the conventional magnetic element 82 even though I2 is lower than I1. Thus, as can be seen by the distributions 95 and 96, for a read current appropriate for the low resistance state, read and write margin may be small.
Large differences for the read currents for the low and high resistance states, in the distributions 96 and 97, are desirable for high speed memory operations. Stated differently, the distribution 96 is desired to be at a significantly larger current than the distribution 97. For example, the distribution 96 may be desired to be centered at one hundred twenty microamperes, while the distribution 97 may be desired to be at approximately sixty microamperes. Furthermore, in order to reduce the size of the selection device 84 and thus the size of the conventional magnetic storage cell 80, the write current is desired to be as small as possible. For example, the distribution 95 may be desired to be centered around two hundred microamperes. Consequently, the difference between writing and reading currents, or the read and write margin, is reduced for a high density memory having a small cell size, particularly for a high speed and large read signal. Because the read and write margins may be small, the read current used may destabilize the state of the magnetic element 82. The read currents used in the distributions 96 or 97 may inadvertently, therefore, write to the conventional spin RAM 70.
Furthermore, a conventional spin RAM memory module, such as would include the conventional spin RAM 70, includes millions to thousands of millions of magnetic elements 82. Process variations may cause the writing and reading currents of the magnetic elements 82 within a conventional spin RAM 70 to have a distribution range. Consequently, the distributions 95, 96, and 97 are depicted as having a width. Stated differently, there may be magnetic elements with write currents between I1 and I2. Similarly, there are magnetic elements having their desired read currents between I1 and I2, between I2 and I3, or below I3. These are called tail distribution bits, or outliers. In addition to process variation caused distribution, thermal effects may also cause variations in read and/or write currents. The magnetic switching process is fundamentally a thermally assisted process, regardless whether the magnetic element 82 is switched by a magnetic field or by a spin polarized electrical current through the spin torque transfer effect. Because of the large number of magnetic memory elements 82 used in a single device chip, and the large number of operating cycles for the whole period of the device product life, thermal assisting can cause the switching writing current for a magnetic element to be much lower than its typical value during a particular cycle. The read current is desired to be even lower than this occasional low writing current. Consequently, the write and read margins may be even smaller. Thus, the possibility of data being compromised during a read operation might be even further increased.
Accordingly, what is desired is a method and system for providing and utilizing memory cells employing spin transfer based switching with improved read and write margin, or reduced reading current induced accidental writing error. The present invention addresses such a need.